1. Field of the Invention
The present invention relates to a monitor and control system, which monitors operation of plural monitor controlled sections in a transmission device. More particularly, it relates to a monitor and control system, which may prevent physical correspondence of interface signals with the controlled sections to be monitored from being complicated, thereby, to simplify access to the controlled sections by software.
1. Description of the Related Art
FIG. 20 shows a structural example of a transmission device. The transmission device includes plural m units #1 to #m, each unit 200 of which includes plural n MPU interface sections #i-1 to #i-n (i=1 to m).
The transmission device further includes a monitor and control section 100, which monitors the plural n MPU interface sections in each of the plural m units, which are monitored and controlled. The monitor and control section 100 is provided on the first unit #1 as a monitor and control package, for example.
Additionally, the monitor and control section 100 informs statuses of the plural n MPU interface sections #i-1 to #i-n in each unit to be monitored to an operation system 300, which is an upper layered device.
FIG. 21 shows a structural example of the conventional monitor and control system in a transmission device, in which MPU interface sections in each unit are monitored on the structure shown in FIG. 20. Especially, a structure in the case where a monitor and control section 100 (hereinafter, it is called as a monitor control package) interfaces with a section 200 to be monitored and controlled (hereinafter, it is called as a monitored and controlled package) by the use of a memory bus communication method.
In FIG. 21, the monitor and control package 100 is provided on the unit #1. Further, n monitored and controlled packages 200 are provided in each unit #1 to #m. Since each unit has the same structure, only a structure of the unit #1 is shown in detail for simplicity.
The monitor and control package 100 consists of a MPU 1, a memory 2 and a chip select generator 3. The memory 2 latches an address transmitted from the MPU 1. These elements are connected by an address bus 10, a data bus 11 and a reading or writing control signal (RD/WR) line 12, which are parallel buses.
The MPU 1 of the monitor and control package 100 and the monitored and controlled package 200 are connected by a chip select (CS) line 13 generated by the chip select (CS) generator 3 in addition to the address bus 10, the data bus 11 and the reading/writing control signal (RD/WR) line 12.
Therefore, a number of physical connections between the monitor and control package 100 and the monitored and controlled package 200 can be expressed as a total of a number of address lines+a number of data lines+a number of control signal lines+a number of chip select lines, i.e., a number n of the monitored and controlled packagesxc3x97a number m of the units.
FIG. 22 shows the other embodiment of the conventional monitor and control system, in which the monitor and control package 100 interfaces with the monitored and controlled package 200 by the use of a serial communication method, in which standard protocols are employed.
The MPU 1 of the monitor control package 100 and the monitored and controlled package 200 are connected by a command signal line 14 and a response signal line 15 through a serial interface circuit 4, which supports a standard protocol.
In other words, command signals transmitted through the address bus 10, the data bus 11 or the reading/writing control signal (RD/WR) line are converted into serial signals through the serial interface circuit 4, and the converted signals are output to each MPU interface section #i-1 to #i-n.
On the other hand, response signals, which are serial signals transmitted from the monitored and controlled package 200 are converted into parallel signals by the serial interface circuit 4, and the converted signals are transmitted to the address bus 10, the data bus 11, or the reading/writing control signal (RD/WR) line 12.
However, when employing a standard protocol on the structure shown in FIG. 22, a protocol sequence becomes necessary, and therefore, it is required to execute the processes on a software.
In here, there are following problems when considering the above-described system shown in FIGS. 21 and 22.
At first, it is a problem that a number of connections between the monitor and control package 100 and the monitored and controlled package 200 is increased.
When eight address lines, eight data bus lines, two control signal lines, five monitored and controlled package 200, and three units are employed, for example, the number of the total number of connections becomes 8+8+2+(5xc3x973)=33.
It should be necessary to place such a large number of line patterns on the monitored and controlled package 200. It may become difficult to wire the patterns because of line congestion with the other high-speed main signals (refer to the unit #1 of FIG. 21).
If monitor and control are required between units (refer to units #2 to #m) in FIG. 21, each unit should be connected to the data bus 10 and the address bus 11 for the MPU 1, the control signal line 12, and a chip select line (CS), respectively, by cables, for example.
Therefore, the number of signal lines for transmitting and receiving between units becomes large, and the number of cables is also increased. That structure can not be used in a real system.
On the other hand, although the number of signal lines can be reduced when employing a serial interface by the use of a communication protocol, as shown in FIG. 22, a burden on a software increases. FIG. 23 shows a structure of a standardized protocol communication. As shown in FIG. 23, the structure has a hierarchical design of seven layers. It is necessary to execute processes with cautiousness of, at least, the lower 2 layers, i.e., physical layer and data link layer, when monitoring and controlling a transmission device.
Therefore, when employing a serial communication method by the use of the standard protocol, a software should execute processes for terminating not a little over head for communication. Therefore, the burden on the software becomes large. As the result, that loads more burden on the software development steps, which require a large number of steps when developing a transmission device or system. That also increases a time of developing the transmission device.
From this view point, it is an object of the present invention to provide a monitor and control system in a transmission device, by which a mounting dimension can be reduced, a consumption power can be lowered, and the cost can be reduced by reducing a number of connectors for connecting between units and a number of driver/receiver ICs.
Further, it is another object of the present invention to provide a monitor and control system in a transmission device, for which a software not depending on a protocol can be developed, a time of developing the system can be reduced, and reliability can be realized.
The above-described objects according to the present invention can be achieved by a monitor and control system in a transmission device, having a monitor and control package, and plural monitored and controlled packages connected to the monitor and control package through serial buses, in which the monitor and control package monitors the plural monitored and controlled packages.
The monitor and control package has a controller, which generates parallel address and data, and a first converter, which converts the parallel address and data generated by the controller into serial address and data, and each of the plural monitored and controlled packages has a second converter, which converts the serial address and data transmitted from the first converter of the monitor and control package through the serial buses into parallel address and data.
It becomes possible to facilitate serial communication of an interface between the monitor and control package and each of the monitored and controlled packages, reduce a number of connection lines of the interface, and complete a communication with one bus cycle of a MPU, which is used as the controller.
Additionally, in one preferred mode, the monitor and control package and each of the monitored and controlled packages respectively have first and second timing generator, and outputs from the first and second timing generators control operations of the corresponding first and second converters.
Alternatively, in another preferred mode, the monitor and control package further has a third converter, which converts the serial data transmitted from the monitored and controlled package into parallel data.
Additionally, each of the monitored and controlled packages further has an address judgement section, which judges whether or not the access is addressed to the monitored and controlled package, according to the parallel addresses, which are converted by the second converter.
Further, in one preferred mode, the monitor and control package and each of the monitored and controlled packages respectively has a parity generator, which generates a parity bit and attaches the parity bit to the parallel address and data, and a parity check section, which checks the parity bit of parallel address and data after converting the received serial address and data into parallel address and data.
It becomes possible to monitor errors on serial buses and realize the reliability according to the feature of the present invention.
Alternatively, in one preferred mode, each of the monitored and controlled packages has a memory access controller, and the memory access controller monitors errors on the serial buses, and inhibits to access the memory of the monitored and controlled packages when an error is found.
Furthermore, in one preferred mode, each of the monitored and controlled packages has a memory access controller, and the memory access controller monitors errors on the serial buses, and inhibits to access the memory of the monitored and controlled packages when an error is found.
Alternatively, the monitor and control package has latch circuits, which latches the parallel address and a parallel signal, which is different from the parallel address, and the outputs from the latch circuits are converted to serial signals at the first converters.
On the structure, the parallel address or the parallel signal, which is different from the parallel data are writing and reading control signals, which access the memory of the monitored and controlled package.
Further, other objects of the present invention will become clear by the description for explaining embodiments according to the attached drawings.